1. Field of the Invention
The present invention relates to a method for detecting redunded defective addresses in a memory device with redundancy.
2. Discussion of the Related Art
In the field of semiconductor memories, it is a common technique to provide redundancy memory elements, such as redundancy word lines and/or bit lines, useful for functionally replacing defective word lines or bit lines. To this purpose, non-volatile memory registers (redundancy registers) must be provided in the memory device for storing the addresses of the defective memory elements (defective addresses), and for comparing a current address supplied to the memory device with the defective addresses stored therein: when the current address coincides with a defective address, the defective memory element is not selected, and a redundancy memory element is instead selected; if this occurs, it is said that the defective memory element has been redunded.
The functional substitution of a redundancy memory element for a defective memory element is completely transparent to the end user, but the memory device manufacturer could be interested in knowing which of the memory elements are defective, i.e. which are the defective addresses.
Conventionally, for implementing this particular test mode, output signals of the redundancy registers (i.e. the signals representative of the condition of coincidence between the current address supplied to the memory device and one of the defective addresses stored therein) are logically OR-ed together and the resulting signal is directly supplied to an output terminal of the memory device; the memory device is sequentially supplied with all the possible address configurations: when the current address configuration coincides with a defective address, a transition is detected at the output terminal, indicating that the current address is a defective address.
This methodology is time consuming, especially for memories of large size: for example, in a byte-wide 16 Mbit device 2.sup.21 different address configurations must be sequentially scanned.
In view of the state of art described, it is an object of the present invention to provide an improved method for detecting redunded defective addresses in a memory device with redundancy which is faster than the conventional method.